Download CMOS Nanoelectronics: Innovative Devices, Architectures, and by Nadine Collaert PDF
By Nadine Collaert
This booklet covers some of the most very important equipment architectures which have been broadly researched to increase the transistor scaling: FinFET. beginning with idea, the publication discusses the benefits and the mixing demanding situations of this equipment structure. It addresses intimately the subjects akin to high-density fin patterning, gate stack layout, and source/drain engineering, that have been thought of demanding situations for the mixing of FinFETs. The ebook additionally addresses circuit-related elements, together with the influence of variability on SRAM layout, ESD layout, and high-T operation. It discusses a brand new equipment inspiration: the junctionless nanowire FET.
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Additional resources for CMOS Nanoelectronics: Innovative Devices, Architectures, and Applications
Doyle B. , Rios R. , “High performance fullydepleted tri-gate CMOS transistors,” IEEE Electron. Device Lett, 24(4), 263–265, 2003. 10. , Korbel A. , “Short-channel vertical sidewall MOSFETs,” IEEE Trans. Electron. Devices, 48(8), 1783– 1788, 2001. 11. , Regolini J. , Pantel R. , “Siliconon-nothing (SON) — An innovative process for advanced CMOS,” IEEE Trans. Electron. Device, 47(11), 2179–2185, 2000. 12. , Carron V. , “Self-aligned planar doublegate MOSFETs by bonding for 22-nm node, with metal gates, high κ dielectrics, and metallic source/drain,” IEEE Electron.
The use of embedded SiGe S/D for pMOS  and Si:C for nMOS has also been demonstrated in MuGFET devices . In SOI MuGFETs, typically the impact on the mobility is small as the recess depth is limited due to the Si ﬁlm thickness. This stressor has shown to be more eﬃcient in planar bulk devices . Finally, all strain need to be compatible with “gate last” processing which is considered the most feasible way of introducing metal gates. Only a small amount of publications have appeared on the latter topic but it can be noticed that the overall trends in MuGFET devices are the same as compared to planar bulk.
9); however, this process was not longer functional for a 22 nm node with a 90 nm ﬁn pitch and 17 nm ﬁn CD target. Three main changes were observed when the dry etching process developed for a 32 nm node was directly applied on a 22 nm node cell: 1) the CD was considerably increased, 11 nm larger than the target CD (17 nm); 2) the ﬁn proﬁle was tapered and, 3) ﬁn sidewalls were heavily attacked, creating a severe side wall roughness (SWR). The CD SEM measurements revealed that during the BARC opening and PR trim step the CD loss was larger on a 90 nm than on a 124 nm pitch (cfr.