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Download Built-in-Self-Test and Digital Self-Calibration for RF SoCs by Sleiman Bou-Sleiman, Mohammed Ismail PDF

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By Sleiman Bou-Sleiman, Mohammed Ismail

This booklet will introduce layout methodologies, often called Built-in-Self-Test (BiST) and Built-in-Self-Calibration (BiSC), which counterpoint the robustness of radio frequency (RF) and millimeter wave (mmWave) built-in circuits (ICs). those circuits are utilized in present and rising conversation, computing, multimedia and biomedical items and microchips. The layout methodologies awarded will bring about bettering the yield (percentage of operating chips in a excessive quantity run) of RF and mmWave ICs so that it will allow profitable production of such microchips in excessive quantity.

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Limited accessibility limits the detectability of faults and restricts observability. This is especially true for the traditional RF testing methods where powerful mixed-signal Automatic Test Equipment (ATE) and benchtop laboratory setups – such as rack-and-stack – require a sizeable investment in terms of actual cost to obtain and maintain, difficulty of interfacing to the internal nodes, and long test times. A promising technique borrowed from digital design and only recently applied to RF is Built-in-Self-Test, or BiST.

Solid-State Circuits, vol. 37, pp. 716–725, 2002 17. A. Helmy and M. Ismail, Substrate Noise Coupling in RFICs. Springer, 2008 18. C. Chiang and J. Kawa, Design for Manufacturability and Yield for Nano-scale CMOS. Springer, 2007 19. P. ” Wiley, 2008 20. M. ” EE Times, 6/13/2008 [Online]. com/electronics-news/4077225/Toppan-rolls-32-nmmasks-but-can-industry-afford-it- Chapter 2 Radio Systems Overview: Architecture, Performance, and Built-in-Test In this chapter, we take a look at RF systems from the system to the block level.

RF detectors, much like the test attenuator and switches, are additional circuits and as such their presence needs to be as non-invasive to the system as possible. This places certain requirements on their design. Multiple detectors can be placed along the transmitter and receiver chains, with their outputs forming a low frequency (mostly dc) bus that can be easily digitized for analysis. Test result analysis: The powerful digital backend can also be used to perform test results analysis. Test results can be derived from two sources: the primary digital lane and the auxiliary dc lane.

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