Download Asynchronous Pulse Logic by Mika M. Nystrom, Alain Martin PDF
By Mika M. Nystrom, Alain Martin
"Asynchronous Pulse common sense is a entire research of a newly constructed asynchronous circuit family members. The ebook covers circuit conception, sensible circuits, layout instruments and an instance of the layout of an easy asynchronous microprocessor utilizing the circuit relatives. Asynchronous Pulse good judgment may be of curiosity to the commercial and educational researcher engaged on high-speed VLSI platforms. Graduate scholars will locate this an invaluable reference for computer-aided layout of asynchronous or similar VLSI structures.
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Additional resources for Asynchronous Pulse Logic
Yes, it is. 6. 85 ns. 0 delays. Since the range of input pulse lengths comfortably contains the range of output pulse lengths, we should have to add considerable load, or we should have to fall victim to extreme manufacturing variations to make the pulse either die out or double up as it travels down a pipeline of pulse repeaters of this kind. Since, further, the input-output relationship of the pulse lengths is almost entirely monotonic, we can summarize the behavior of the pulse repeater thus: 8 Note that the various shmoo plots and the width-gain plot are drawn for several different circuits, so the numerical values are not necessarily directly comparable across them; also the criterion for a pulse’s being legitimate is somewhat over-strict in the shmoo plots.
Asynchronous-circuit design-styles inherently require that the logic computations carry timing information. This can mean either that the computations explicitly carry timing information (as in QDI or speed-independent design) or that implicit timing-assumptions are made (as in bundled-data design); from the historical trends in synchronous design, we may infer that we need not apologize for the mixing of timing and logic—everyone that builds fast circuits mixes. Nor should we be surprised to find out that the subtleties of asynchronous pulse-logic are due mainly to dependencies between logic and timing.
13 (as usual, we have ignored the irrelevant time-translation of the various signals). The pulse repeater whose behavior we are plotting must be avoided because it misbehaves: the weaker input-pulse causes a stronger output-pulse. Both A and B are slightly longer than hence there will be some interference on the node during the later parts of the input pulses. The pulse in A is slightly “weaker” than in B during the first as shown by the notch at the top; we have assumed in the waveform that the weak merely causes a slow transition.